The invention relates to an integrated field-effect transistor memory comprising a sense amplifier which includes a parallel connection of a first and a second current branch, each current branch comprising a channel of a control transistor and a channel of a load transistor, which channels are coupled via a junction point, the junction point in each current branch being coupled to the gate of the load transistor in the other current branch, at least one of said junction points constituting an output of the sense amplifier.
An integrated memory of this kind is known from JP Kokai 61-96587. The memory described therein comprises sense amplifiers in which the channels of two cross-wise coupled P-type field-effect transistors Q3 and Q4 are connected to the supply voltage VDD and the drains of respective N-type field-effect transistors Q1 and Q2. The bit line voltages in integrated memory circuits usually approximate the positive supply voltage. Consequently, sense amplifiers of this kind have the drawback that the voltages on the drains of the transistors Q1 and Q2 may decrease only from 1 to 2 V below the positive supply voltage in order to ensure that the control transistors Q1 and Q2 are operative exclusively in the saturation zone so as to achieve an optimum operating speed. In the event of disturbances (VDD bumps) in the positive supply voltage in the negative direction in the known sense amplifiers, however, the setting of at least one of the transistors Q1 and Q2 will still leave the saturation zone, so that such sense amplifiers become slower.